Lecture: The Era of Chiplets and its Impact to Future System Designs

Tobias Webel (IBM)

Lecture Slides

Moore's Law, which predicts that the number of transistors on a microchip will double every 18 to 24 months, is still a guiding principle in the design and manufacture of computer hardware. While some experts have predicted that Moore's Law may eventually reach its limits due to the physical constraints of semiconductor technology, many others believe that new innovations and approaches will continue to push the boundaries of what is possible.

One innovation area which is currently heavily pursued by key Hardware companies is the so called chiplet approach. Chiplets are small, modular components that can be combined to create larger, more complex systems. They allow for greater flexibility and customization in the design of integrated circuits, and can also help to reduce costs and increase efficiency. Chiplets have become increasingly popular in recent years, and are expected to play a major role in the development of future computing systems.

Intel CEO Pat Gelsinger promised at company event that "Moore's law is alive and well," adding that “we are predicting that we will maintain or even go faster than Moore's law for the next decade.

This lecture will introduce the chiplet concept, addresses opportunities and challenges of the chiplet approach and will share insights in how the industry moves forward with an openness and standardization.

Tobias Webel (IBM)

Tobias Webel leads the Service Infrastructure and Secure Boot Processor Hardware Development for IBM zSystems and POWER brand. In addition, he leads the Power Management Processor Hardware Development for IBM zSystems.

He received his diploma (Dipl.-Ing.) in Electrical Engineering from the University of Stuttgart in the Year 1995. In the same year he joined the IBM Research and Development Lab in Boeblingen, Germany as a Hardware Logic Design Engineer. During his entire technical career in IBM, he was focused on Processor and System Hardware Development responsible for Reliability, Availability and Serviceability (RAS) of IBM Enterprise Class Systems.

In the Year 2016 he was appointed as Senior Technical Staff Member (STSM) in the IBM Infrastructure Division. He holds 36 Patents and is author and co-author of 19 publications.